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Features

Epitaxial planar die construction.
Complementary Pair.
eUltra-small surface mount package.
One 2222A-Type NPN,

One 2907A-Type PNP
ldeal for low power amplification and switching.

MMDT2227 SOT-363_00.jpg

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2024-12-20TSMC's Kumamoto factory will begin mass production within this year, utilizing 22/28nm and 12/16nm process technologies to manufacture logic ICs.
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2024-12-17TSMC has publicly unveiled its 2nm process, which increases transistor density by 15% compared to the 3nm chips, boosts performance by 15% at the same power consumption, and reduces power consumption by 24-35% for the same performance.
2024-12-16CATL and Stellantis are planning to build a joint venture battery factory in Zaragoza, Aragon, Spain, with Stellantis as the primary customer. The total construction period is expected to last four years
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2024-12-12TSMC is expected to certify an ultra-large version of its CoWoS (Chip-on-Wafer) packaging technology by 2027. This technology will offer intermediate layer sizes of up to nine mask sizes and support 12 HBM4 memory stacks. It is speculated that it will be adopted by ultra-high-end AI processors between 2027 and 2028.
2024-12-11TSMC's 2nm process trial production results show a yield rate exceeding 60%, with plans to begin mass production of 2nm chips next year

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