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Maximum ratings( Ta=25℃ unless otherwise noted)

Parameter	Symbol	Value	Unit
Drain-SourceVoltage	VDS	60	V
Gate-SourceVoltage	VGS	±20	V
ContinuousDrainCurrent	ID	3	A
PulsedDiodeCurren	IDM	10
ContinuousSource-DrainCurrent(DiodeConduction)	IS	0.76
PowerDissipation	PD	1.25	W

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2024-12-20TSMC's Kumamoto factory will begin mass production within this year, utilizing 22/28nm and 12/16nm process technologies to manufacture logic ICs.
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2024-12-17TSMC has publicly unveiled its 2nm process, which increases transistor density by 15% compared to the 3nm chips, boosts performance by 15% at the same power consumption, and reduces power consumption by 24-35% for the same performance.
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2024-12-12TSMC is expected to certify an ultra-large version of its CoWoS (Chip-on-Wafer) packaging technology by 2027. This technology will offer intermediate layer sizes of up to nine mask sizes and support 12 HBM4 memory stacks. It is speculated that it will be adopted by ultra-high-end AI processors between 2027 and 2028.
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