Manufacture:

TAPEOUT (TO): Refers to submitting the final GDSII files to the foundry for manufacturing.

FULL MASK: Refers to all masks used in the manufacturing process being tailored for a specific design.

MPW (Multi Project Wafer):  Multiple projects sharing the same wafer, meaning a single manufacturing process can handle production tasks for multiple IC designs simultaneously.

MPW (Multi-Project Wafer) involves sharing a mask set with other parties, whereas FULL MASK entails exclusive use of a mask set. For higher-risk chips, starting with MPW allows testing before committing to FULL MASK production if everything checks out.

SEAT：In an MPW run, the minimum area available is akin to seats on a "shuttle"， where participants can select one or several "seats." Each "seat" corresponds to 3mm x 4mm of space.

Foundry :  Manufacturers specializing in chip fabrication, such as TSMC, SMIC, and UMC, are known as foundries. In contrast, fabless companies, which include design houses without fabrication facilities, rely on these foundries for production.

Wafer：A wafer is a thin, round slice of semiconductor material used as the foundation for manufacturing integrated circuits.

Die：After wafer dicing, each individual chip needs to be encapsulated in a package to become a functional microchip.

Chip：The final packaged chip.

Bump："Bumping" refers to the formation of solder bumps. After growing bumps (such as gold, tin-lead, or lead-free) on the wafer surface, it is commonly used for flip-chip packaging processes.

Wirebonding：Wire bonding, also known as wire bonding or wire interconnection, refers to the process of using metal wires (such as gold or aluminum wires) and applying heat or ultrasonic energy to establish solid-state connections within integrated circuits, linking chips to circuitry or lead frames.

Flipchip：Flip chip, also known as direct chip attachment, involves depositing solder bumps on I/O pads. The chip is then flipped and heated to melt the solder bumps, creating connections with the ceramic substrate.

CP(Chip Probing)：Direct wafer testing involves testing each individual Die on the entire wafer to ensure that each Die meets the basic device characteristics or design specifications. This typically includes verification of voltage, current, timing, and functionality. It serves to assess the manufacturing process capabilities of the fab facility.

FT(FinalTest)：It is the last step before a chip leaves the factory. It involves testing packaged chips, which are tested after completion of the CP (Chip Probe) test and packaging. FT testing is used to assess the packaging facility's manufacturing capabilities.

For wafer-level CP testing, if a Die is found to be defective, it avoids the unnecessary costs of packaging and substrate.

After CP testing is completed, there is still a possibility of chip failure during the packaging process. Therefore, FT testing is necessary to identify and remove any failed chips.

Yield ：The yield of chips is closely tied to the manufacturing process. Chips have a probability of failure, which increases with their size—the larger the chip, the higher the likelihood of failure.

IP（Intellectual Property）：In integrated circuit design, it refers to the complete functional module of a verified, reusable, and function-specific integrated circuit.

IP can be classified by licensing terms into two categories: License and Loyalty.

License: Permission to use this IP, granted by its licensing terms.

Royalty: After users utilize this IP, royalties are due per chip.

IP constitutes the fundamental building blocks of chips, such as USB, PCIe, CPU, and others. The entire chip integrates these IPs, enabling complex functionalities. The essence lies in IP reuse, crucial for developing chips with tens of millions or even billions of gates.

SOC（System On Chip)：System On Chip (SoC) integrates components like CPU, bus, peripherals, etc., into a single chip. For instance, a smartphone processor exemplifies a sophisticated SoC.

Design：

Register-Transfer Level（RTL) ：It is a hardware description language used to describe synchronous digital circuits.

Netlist：RTL needs to be synthesized into a netlist before it can become a gate-level design.

SDC（Synopsys Design Chip) ：SDC is a file provided by the design that synthesis tools require to convert RTL into a netlist. Key aspects described in the SDC include chip operating frequency, chip IO timing, design rules, special paths, and paths exempt from checking, among others.

Freeze：It means it cannot be changed anymore. For example, "RTL freeze" indicates the code has been finalized, and "netlist freeze" means the netlist has been locked and cannot be further modified.

Verification：The main focus is on chip verification methodology, ensuring consistency between verifying RTL and the reference model.

Simulation：Simulation typically involves generating waveforms that intuitively reflect real-world scenarios, including chip functionality, verification, and power consumption.