On September 12th, TSMC's interim board of directors approved two resolutions. One is to subscribe for Arm common stock for an amount not exceeding $100 million, and the other is to invest in IMS Nanofabrication GmbH, a subsidiary of Intel and a semiconductor equipment manufacturer, acquiring a 10% stake within the limit of $432.8 million.

TSMC Chairman Mark Liu stated that Arm is an important part of the semiconductor ecosystem, and TSMC hopes for the success of Arm. It is believed that TSMC's investment in Arm will help expand its advantage in wafer foundry follow-up orders, as the Arm architecture is the most important design foundation for the global chip industry.

Compared to the investment in Arm, this article pays more attention to TSMC's investment in IMS. Zhang Xiaoqiang, Senior Vice President of Business Development at the leading wafer foundry, pointed out that since 2012, TSMC has been cooperating with IMS in the development of multi-beam mask writers for advanced processes. This investment will continue the long-term partnership between TSMC and IMS, accelerating innovation and achieving deeper cross-industry collaboration. The relevant transaction process is expected to be completed in the fourth quarter of 2023.

Intel stated that it still holds the majority stake in IMS, and IMS will operate as an independent subsidiary under the leadership of CEO Elmar Platzgummer.

In addition to TSMC, Intel has also agreed to sell a 20% stake in IMS to Bain Capital, a global top-tier investment firm, which is expected to be completed in the third quarter of this year.

Why are leading semiconductor companies like Intel and TSMC, as well as top global investment institutions like Bain Capital, eager to get close to a small company like IMS? The main reason is that the development of advanced processes is becoming increasingly challenging, and the dependency on high-precision semiconductor equipment is increasing, especially for high numerical aperture EUV lithography machines, which have an elevated industry status. Multi-beam mask writers are closely related to EUV equipment and their relevance is growing. In simple terms, lithography requires the use of masks (reticles), and multiple layers of masks are needed. Multi-beam mask writers are advanced equipment used by wafer fabs to manufacture masks used in production lines.

I. Introduction to Lithography Process

The role of a lithography machine is to accurately project the pattern on the photomask onto the silicon wafer in proportion, completing the first step of the integrated circuit manufacturing process, which is graphical transfer. Afterwards, through steps such as developing, etching, stripping, and cleaning, a solid integrated circuit is manufactured on the silicon wafer.

EUV lithography is actually a complex and precise projection technology. After undergoing lithography, a single wafer completes the exposure work for billions of chips, and the efficiency is very high, far exceeding other technological routes (such as nanoimprint).

To manufacture a chip, multiple layers of lithography are required, and each layer requires a photomask. Generally, the bottom 1-2 layers require the highest resolution and the most stringent lithography precision. Advanced lithography machines are needed to complete the exposure process. However, the upper layers such as the metal layers do not require high precision and the photomasks are relatively simple, so lithography machines with larger line widths can be used. Therefore, lithography machines with different levels of precision can be used in combination to complete the exposure work for the entire chip. The most advanced lithography machine is only responsible for the exposure work at the finest line width.

One more thing, before EUV, in order to manufacture 22nm, 16nm, and 14nm integrated circuits, multiple-exposure technology was needed due to the lack of high-precision lithography machines. There are several types, mainly including LELE, LFLE, SADP/SAQP. Regardless of which exposure technology is used, it is to achieve smaller feature sizes under the limited resolution of the lithography machine. Among them, SAQP has the best effect, followed by SADP, and LELE and LFLE are about the same. Multiple-exposure means multiple exposures, and a new photomask is required for each exposure.

II. Introduction to Photomask

A photomask is a graphic template commonly used in micro and nano fabrication processes in lithography. It consists of an opaque mask pattern formed on a transparent substrate using thin films. The pattern information is then transferred onto a silicon wafer through exposure.

Photomask manufacturers produce blank masks, which are typically made of 6 x 6-inch glass substrates coated with metal films and photosensitive agents. After purchasing these blank products, semiconductor fabs use various types and grades of lithography machines to write the information of the integrated circuits (mature or advanced process) they want to manufacture onto the blank masks (this is known as patterning). The patterned masks are then placed into dedicated reticles and loaded onto lithography machines, which project the integrated circuit patterns from the masks onto the silicon wafers. Subsequently, the wafers go through processes such as development and etching.

As can be seen, photomasks are the initial step in manufacturing integrated circuits and are crucially important. If this step is not done well, it will impact the subsequent process flow and ultimately affect the performance and yield of the final chips. In advanced process nodes below 7nm, multiple exposures and multi-layer intricate masks are required, placing higher demands on the related equipment.

Each individual chip design comes with a set of photomasks. The cost at the 3nm process node can be as high as $50 million. Not only do new designs require new photomasks, but existing designs also need replacements because masks can develop defects over time and need repair or new manufacturing.

Taking the latest iPhone 15 Pro by Apple as an example, its core processor A17 Pro adopts Taiwan Semiconductor Manufacturing Company's latest version of the 3nm process, which requires 25 layers of EUV lithography, twice as many as the N5 (the initial version of 5nm). Each layer requires a photomask, indicating increasingly higher requirements for the corresponding products and equipment.

To be continued...